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HQ 559071





August 24, 1995

CLA-2 R:C:S 559071 DEC

CATEGORY: CLASSIFICATION

TARIFF NO.: 9802.00.80

District Director of Customs
P.O. Box 789
Great Falls, Montana 54903

RE: Request for Internal Advice; Wafers incorporating integrated circuits;
United States v. Texas Instruments Inc., C.A.D. 1178, 545 F. 2d 739;
HRL 555638

Dear Sir/Madam:

This is in response to your request for Internal Advice, by letter dated February 28, 1995, regarding the eligibility of silicon wafers used in the production of integrated circuits for a partial duty exemption pursuant to subheading 9802.00.80, Harmonized Tariff Schedule of the United States (HTSUS).

FACTS:

In the United States, a high grade silicon is produced from pure crystal silicon in a supersaturated silicon solution contained in a cylinder four inches in diameter. After the silicon crystallizes throughout the length of the cylinder, the solid cylindrical mass is removed and is sawed into thin slices. These slices are called wafers. Each wafer is subjected to various treatments resulting in integrated circuits (also known as die) embedded into the surface of the wafer. On the surface of the wafer, the integrated circuits appear in regular rows and columns. Depending on the size of the particular circuit, the number of circuits per wafer may range from very few to several hundred. The circuits are generated through various processes.

One process results from placing a photomask over the surface of the wafer and passing a strong light through the mask. The mask is patterned in clear and opaque material to let the light through in a pattern dictated by the end use of the integrated circuit. The light affects the surface of the wafer so that, by the application of the etching chemical, some wafer surface is removed. Various finishing processes are
applied to finish the integrated circuit. After the circuit is finished, testing is conducted. Bad integrated circuits are marked with a colored paint. Lines are drawn on the wafers as a pattern used for later scribing of the wafer overseas. These lines are drawn in regular vertical and horizontal rows and columns so that the integrated circuits are framed. The wafers are then exported overseas from the United States for processing.

At the foreign processing facility, a sticky paper is applied to the bottom of the wafer. The wafers are then scribed along the pre-drawn lines using a small circular diamond saw. This scribing process with circular saw passes through the wafer completely. A machine called a die bonder is passed over the broken wafer and sucks up all the material on the sticky paper except the good die. The good die are then removed and inserted into the lead frames where they are glued to a small pad on the bottom of the frame. Lead frames are small metal containers which have electrical leads protruding from their bottom. After the die are placed in their frames, gold wire is placed near the upper extremity of the die and an ultrasound device operates to generate heat which causes the wire to be soldered to the die. The gold wire extends to the bottom of the lead frame where the soldering process is repeated. This process is repeated around the sides of the die until all soldering is accomplished. Each point of soldering on the lead frame electrically connects the die to the external leads.

Molten plastic is poured over the die and lead frame which when solidified forms a protective surface and an electrically insulating barrier. The encapsulated die is then returned to the United States. This finished product is placed on a printed circuit board during a manufacturing process and is electrically connected via the leads extending from the lead frame.

ISSUE:

Are the wafers described above eligible for the partial duty exemption pursuant to subheading 9802.00.80, HTSUS, when returned to the United States?

LAW AND ANALYSIS:

Subheading 9802.00.80, HTSUS, provides a partial duty exemption for

(a)rticles . . . assembled abroad in whole or in part of fabricated components, the product of the United States, which (a) were exported in condition ready for assembly without further fabrication, (b) have not lost their physical identity in such articles by change in form, shape or otherwise, and

(c) have not been advanced in value or improved in condition abroad except by being assembled and except by operations incidental to the assembly process such as cleaning, lubricating, and painting

All three requirements of subheading 9802.00.80, HTSUS, must be satisfied before a component may receive a duty allowance. An article entered under this tariff provision is subject to duty upon the full cost or value of the imported assembled article, less the cost or value of the United States components assembled abroad, provided the section 10.24, Customs Regulations (19 CFR 10.24), documentary requirements are satisfied.

Section 10.14(a), Customs Regulations (19 CFR 10.14(a)), states, in part, that

The components must be in condition ready for assembly without further fabrication at the time of their exportation from the United States to qualify for the exemption. Components will not lose their entitlement to the exemption by being subjected to operations incidental to the assembly either before, during, or after their assembly with other components.

Section 10.14 contains an example that states where integrated circuit wafers containing individual integrated circuits have been scribed or scored in the United States, these articles are regarded as fabricated components. The example goes on to provide that separating the wafer into individual frames by cutting or the segmentation of the wafer into individual die by flexing or breaking along the scored lines is regarded as an operation incidental to the assembly process. Section 10.16(c), Customs Regulations (19 CFR 10.16(c)), states that any significant process, operation or treatment whose primary purpose is the fabrication, completion, physical or chemical improvement of a component precludes the application of the exemption under subheading 9802.00.80, HTSUS, to that component.

The facts presented in United States v. Texas Instruments Inc., C.A.D. 1178, 545 F. 2d 739 (1976) are very similar to those you have presented in your Internal Advice request. The Texas Instrument case involved the production of transistors from silicon in a manner very similar to the method described above. The foreign assembly process involved the scoring of the silicon slice along the marks established in the United States. Each chip was then bonded to three stiff lead wires. This completed assembly was then molded in a plastic compound using a mold press. The appellate court held that the scribing operation and the separation of the transistor chips into separate individual transistor areas did not amount to a further fabrication. In
addition, the court concluded that the scribing and breaking operations at issue were incidental to the assembly process within the meaning of clause (c) of the statute. See also Headquarters Ruling Letter (HRL) 555638, dated June 11, 1990. Consistent with the holding in Texas Instruments and the example in 19 CFR 10.16(a), we find that the scribing of the wafers in this case along pre-drawn lines is an operation incidental to the foreign assembly process.

HOLDING:

Consistent with the position articulated in United States v. Texas Instruments Inc., C.A.D. 1178, 545 F. 2d 739 (1976), an allowance in duty may be made under subheading 9802.00.80, HTSUS, with respect to the cost or value of the U.S. components (i.e. the wafer) since the processing performed abroad with respect to the exported wafer are qualifying assembly operations and operations incidental thereto.

This decision should be mailed by your office to the affected importer no later than 60 days from the date of this letter. On that date, the Office of Regulations and Rulings will take steps to make the decision available to Customs personnel via the Customs Rulings Module in ACS and the public via the Diskette Subscription Service, LEXIS, Freedom of Information Act and other public access channels.

Sincerely,

John Durant, Director
Commercial Rulings Division


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