Hi I'm new to verilog I wanted to create a pattern...

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Question by verilog keen
Submitted on 1/31/2006
Related FAQ: FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)
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Hi I'm new to verilog I wanted to create a pattern generator which will get start and odd as input signals in addiction to clock and generate 2 outputs (10 bit) when odd=1 at every clock pulse viz out1 with series like 0,2,8,10,16 out2 with series like 4,6,12,14,20 or outputs when odd is 0 at every clock pulse viz out1 with series like 1,3,9,11,17 out2 with series like 5,7,13,15,21 It looks quite simple with odd and even things but to generate the series whose output is to be transfered every clock pulse makes is difficult to use for or while loop for me,I tried with FSM and am working on it now,can anybody provide me with helping hand

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<< Back to: FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)

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