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Can anyone show me the code to signed arithmetic shift

<< Back to: FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)

Question by nm
Submitted on 5/19/2004
Related FAQ: FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)
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Can anyone show me the code to signed arithmetic shift


Answer by umairsiddiqui
Submitted on 6/12/2005
Rating: Not yet rated Rate this answer: Vote
well sir this my vhdl design of shifter...
can be "easily" converted to verilog....

/////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Shifter1 is
   port
   (
      A_in : in std_logic_vector(15 downto 0);
      B_in : in std_logic_vector(3 downto 0);
      Carry_in : in std_logic;
      Opsel_in : in std_logic_vector(2 downto 0);
      Result_out : out std_logic_vector(15 downto 0);
      Carry_out : out std_logic
   );

end Shifter1;

architecture Behavioral of Shifter1 is
   signal shltemp, shrtemp, saltemp, sartemp, roltemp,
          rortemp, rcltemp, rcrtemp, carry_result : std_logic_vector(16 downto 0);
begin
   ShiftLogicalLeft: process(A_in, B_in, Carry_in) is
   begin
      case B_in is
         when "0000" => shltemp <= Carry_in & A_in(15 downto 0);
         when "0001" => shltemp <= A_in(15) & A_in(14 downto 0) & "0";
         when "0010" => shltemp <= A_in(14) & A_in(13 downto 0) & "00";
         when "0011" => shltemp <= A_in(13) & A_in(12 downto 0) & "000";
         when "0100" => shltemp <= A_in(12) & A_in(11 downto 0) & "0000";
         when "0101" => shltemp <= A_in(11) & A_in(10 downto 0) & "00000";
         when "0110" => shltemp <= A_in(10) & A_in(09 downto 0) & "000000";
         when "0111" => shltemp <= A_in(09) & A_in(08 downto 0) & "0000000";
         when "1000" => shltemp <= A_in(08) & A_in(07 downto 0) & "00000000";
         when "1001" => shltemp <= A_in(07) & A_in(06 downto 0) & "000000000";
         when "1010" => shltemp <= A_in(06) & A_in(05 downto 0) & "0000000000";
         when "1011" => shltemp <= A_in(05) & A_in(04 downto 0) & "00000000000";
         when "1100" => shltemp <= A_in(04) & A_in(03 downto 0) & "000000000000";
         when "1101" => shltemp <= A_in(03) & A_in(02 downto 0) & "0000000000000";
         when "1110" => shltemp <= A_in(02) & A_in(01 downto 0) & "00000000000000";
         when "1111" => shltemp <= A_in(01) & A_in(00)          & "000000000000000";
         when others => shltemp <= (others => '0');
      end case;
   end process;
  
   ShiftLogicalRight: process(A_in, B_in, Carry_in) is
   begin
      case B_in is
         when "0000" => shrtemp <= Carry_in & A_in(15 downto 0);
         when "0001" => shrtemp <= A_in(00) & "0"                  & A_in(15 downto 01);
         when "0010" => shrtemp <= A_in(01) & "00"                 & A_in(15 downto 02);
         when "0011" => shrtemp <= A_in(02) & "000"                & A_in(15 downto 03);
         when "0100" => shrtemp <= A_in(03) & "0000"               & A_in(15 downto 04);
         when "0101" => shrtemp <= A_in(04) & "00000"             & A_in(15 downto 05);
         when "0110" => shrtemp <= A_in(05) & "000000"            & A_in(15 downto 06);
         when "0111" => shrtemp <= A_in(06) & "0000000"           & A_in(15 downto 07);
         when "1000" => shrtemp <= A_in(07) & "00000000"          & A_in(15 downto 08);
         when "1001" => shrtemp <= A_in(08) & "000000000"        & A_in(15 downto 09);
         when "1010" => shrtemp <= A_in(09) & "0000000000"       & A_in(15 downto 10);
         when "1011" => shrtemp <= A_in(10) & "00000000000"      & A_in(15 downto 11);
         when "1100" => shrtemp <= A_in(11) & "000000000000"     & A_in(15 downto 12);
         when "1101" => shrtemp <= A_in(12) & "0000000000000"   & A_in(15 downto 13);
         when "1110" => shrtemp <= A_in(13) & "00000000000000"  & A_in(15 downto 14);
         when "1111" => shrtemp <= A_in(14) & "000000000000000" & A_in(15);
         when others => shrtemp <= (others => '0');
      end case;
   end process;
  
   ShiftArithmaticLeft: saltemp <= shltemp;
  
   ShiftArithmaticRight: process(A_in, B_in, Carry_in) is
      variable s : std_logic;
   begin
         s := A_in(15);
      case B_in is  
         when "0000" => sartemp <= Carry_in & A_in(15 downto 0);
         when "0001" => sartemp <= A_in(00) & s                                                         & A_in(15 downto 01);
         when "0010" => sartemp <= A_in(01) & s & s                                                     & A_in(15 downto 02);
         when "0011" => sartemp <= A_in(02) & s & s & s                                                 & A_in(15 downto 03);
         when "0100" => sartemp <= A_in(03) & s & s & s & s                                             & A_in(15 downto 04);
         when "0101" => sartemp <= A_in(04) & s & s & s & s & s                                         & A_in(15 downto 05);
         when "0110" => sartemp <= A_in(05) & s & s & s & s & s & s                                     & A_in(15 downto 06);
         when "0111" => sartemp <= A_in(06) & s & s & s & s & s & s & s                                 & A_in(15 downto 07);
         when "1000" => sartemp <= A_in(07) & s & s & s & s & s & s & s & s                             & A_in(15 downto 08);
         when "1001" => sartemp <= A_in(08) & s & s & s & s & s & s & s & s & s                         & A_in(15 downto 09);
         when "1010" => sartemp <= A_in(09) & s & s & s & s & s & s & s & s & s & s                     & A_in(15 downto 10);
         when "1011" => sartemp <= A_in(10) & s & s & s & s & s & s & s & s & s & s & s                 & A_in(15 downto 11);
         when "1100" => sartemp <= A_in(11) & s & s & s & s & s & s & s & s & s & s & s & s             & A_in(15 downto 12);
         when "1101" => sartemp <= A_in(12) & s & s & s & s & s & s & s & s & s & s & s & s & s         & A_in(15 downto 13);
         when "1110" => sartemp <= A_in(13) & s & s & s & s & s & s & s & s & s & s & s & s & s & s     & A_in(15 downto 14);
         when "1111" => sartemp <= A_in(14) & s & s & s & s & s & s & s & s & s & s & s & s & s & s & s & A_in(15);
         when others => sartemp <= (others => '0');
      end case;
   end process;
  
   RotateLeft: process(A_in, B_in, Carry_in) is
   begin
      case B_in is
         when "0000" => roltemp <= Carry_in & A_in(15 downto 0);
         when "0001" => roltemp <= A_in(15) & A_in(14 downto 0) & A_in(15);
         when "0010" => roltemp <= A_in(14) & A_in(13 downto 0) & A_in(15 downto 14);
         when "0011" => roltemp <= A_in(13) & A_in(12 downto 0) & A_in(15 downto 13);
         when "0100" => roltemp <= A_in(12) & A_in(11 downto 0) & A_in(15 downto 12);
         when "0101" => roltemp <= A_in(11) & A_in(10 downto 0) & A_in(15 downto 11);
         when "0110" => roltemp <= A_in(10) & A_in(09 downto 0) & A_in(15 downto 10);
         when "0111" => roltemp <= A_in(09) & A_in(08 downto 0) & A_in(15 downto 09);
         when "1000" => roltemp <= A_in(08) & A_in(07 downto 0) & A_in(15 downto 08);
         when "1001" => roltemp <= A_in(07) & A_in(06 downto 0) & A_in(15 downto 07);
         when "1010" => roltemp <= A_in(06) & A_in(05 downto 0) & A_in(15 downto 06);
         when "1011" => roltemp <= A_in(05) & A_in(04 downto 0) & A_in(15 downto 05);
         when "1100" => roltemp <= A_in(04) & A_in(03 downto 0) & A_in(15 downto 04);
         when "1101" => roltemp <= A_in(03) & A_in(02 downto 0) & A_in(15 downto 03);
         when "1110" => roltemp <= A_in(02) & A_in(01 downto 0) & A_in(15 downto 02);
         when "1111" => roltemp <= A_in(01) & A_in(00)          & A_in(15 downto 01);
         when others => roltemp <= (others => '0');
      end case;
   end process;  

   RotateRight: process(A_in, B_in, Carry_in) is
   begin
      case B_in is
         when "0000" => rortemp <= Carry_in & A_in(15 downto 0);
         when "0001" => rortemp <= A_in(00) & A_in(00) & A_in(15 downto 1);
         when "0010" => rortemp <= A_in(01) & A_in(01 downto 0) & A_in(15 downto 02);
         when "0011" => rortemp <= A_in(02) & A_in(02 downto 0) & A_in(15 downto 03);
         when "0100" => rortemp <= A_in(03) & A_in(03 downto 0) & A_in(15 downto 04);
         when "0101" => rortemp <= A_in(04) & A_in(04 downto 0) & A_in(15 downto 05);
         when "0110" => rortemp <= A_in(05) & A_in(05 downto 0) & A_in(15 downto 06);
         when "0111" => rortemp <= A_in(06) & A_in(06 downto 0) & A_in(15 downto 07);
         when "1000" => rortemp <= A_in(07) & A_in(07 downto 0) & A_in(15 downto 08);
         when "1001" => rortemp <= A_in(08) & A_in(08 downto 0) & A_in(15 downto 09);
         when "1010" => rortemp <= A_in(09) & A_in(09 downto 0) & A_in(15 downto 10);
         when "1011" => rortemp <= A_in(10) & A_in(10 downto 0) & A_in(15 downto 11);
         when "1100" => rortemp <= A_in(11) & A_in(11 downto 0) & A_in(15 downto 12);
         when "1101" => rortemp <= A_in(12) & A_in(12 downto 0) & A_in(15 downto 13);
         when "1110" => rortemp <= A_in(13) & A_in(13 downto 0) & A_in(15 downto 14);
         when "1111" => rortemp <= A_in(14) & A_in(14 downto 0) & A_in(15);
         when others => rortemp <= (others => '0');
      end case;
   end process;

   RotateCarryLeft: process(A_in, B_in, Carry_in) is
   begin
      case B_in is
         when "0000" => rcltemp <= Carry_in & A_in(15 downto 0);
         when "0001" => rcltemp <= A_in(15) & A_in(14 downto 0) & Carry_in;
         when "0010" => rcltemp <= A_in(14) & A_in(13 downto 0) & Carry_in & A_in(15);
         when "0011" => rcltemp <= A_in(13) & A_in(12 downto 0) & Carry_in & A_in(15 downto 14);
         when "0100" => rcltemp <= A_in(12) & A_in(11 downto 0) & Carry_in & A_in(15 downto 13);
         when "0101" => rcltemp <= A_in(11) & A_in(10 downto 0) & Carry_in & A_in(15 downto 12);
         when "0110" => rcltemp <= A_in(10) & A_in(09 downto 0) & Carry_in & A_in(15 downto 11);
         when "0111" => rcltemp <= A_in(09) & A_in(08 downto 0) & Carry_in & A_in(15 downto 10);
         when "1000" => rcltemp <= A_in(08) & A_in(07 downto 0) & Carry_in & A_in(15 downto 09);
         when "1001" => rcltemp <= A_in(07) & A_in(06 downto 0) & Carry_in & A_in(15 downto 08);
         when "1010" => rcltemp <= A_in(06) & A_in(05 downto 0) & Carry_in & A_in(15 downto 07);
         when "1011" => rcltemp <= A_in(05) & A_in(04 downto 0) & Carry_in & A_in(15 downto 06);
         when "1100" => rcltemp <= A_in(04) & A_in(03 downto 0) & Carry_in & A_in(15 downto 05);
         when "1101" => rcltemp <= A_in(03) & A_in(02 downto 0) & Carry_in & A_in(15 downto 04);
         when "1110" => rcltemp <= A_in(02) & A_in(01 downto 0) & Carry_in & A_in(15 downto 03);
         when "1111" => rcltemp <= A_in(01) & A_in(00) & Carry_in & A_in(15 downto 02);
         when others => rcltemp <= (others => '0');
      end case;
   end process;

   RotateCarryRight: process(A_in, B_in, Carry_in) is
   begin
      case B_in is
         when "0000" => rcrtemp <= Carry_in & A_in(15 downto 0);
         when "0001" => rcrtemp <= A_in(00) & Carry_in & A_in(15 downto 1);
         when "0010" => rcrtemp <= A_in(01) & A_in(0) & Carry_in & A_in(15 downto 2);
         when "0011" => rcrtemp <= A_in(02) & A_in(01 downto 0) & Carry_in & A_in(15 downto 03);
         when "0100" => rcrtemp <= A_in(03) & A_in(02 downto 0) & Carry_in & A_in(15 downto 04);
         when "0101" => rcrtemp <= A_in(04) & A_in(03 downto 0) & Carry_in & A_in(15 downto 05);
         when "0110" => rcrtemp <= A_in(05) & A_in(04 downto 0) & Carry_in & A_in(15 downto 06);
         when "0111" => rcrtemp <= A_in(06) & A_in(05 downto 0) & Carry_in & A_in(15 downto 07);
         when "1000" => rcrtemp <= A_in(07) & A_in(06 downto 0) & Carry_in & A_in(15 downto 08);
         when "1001" => rcrtemp <= A_in(08) & A_in(07 downto 0) & Carry_in & A_in(15 downto 09);
         when "1010" => rcrtemp <= A_in(09) & A_in(08 downto 0) & Carry_in & A_in(15 downto 10);
         when "1011" => rcrtemp <= A_in(10) & A_in(09 downto 0) & Carry_in & A_in(15 downto 11);
         when "1100" => rcrtemp <= A_in(11) & A_in(10 downto 0) & Carry_in & A_in(15 downto 12);
         when "1101" => rcrtemp <= A_in(12) & A_in(11 downto 0) & Carry_in & A_in(15 downto 13);
         when "1110" => rcrtemp <= A_in(13) & A_in(12 downto 0) & Carry_in & A_in(15 downto 14);
         when "1111" => rcrtemp <= A_in(14) & A_in(13 downto 0) & Carry_in & A_in(15);
         when others => rcrtemp <= (others => '0');
      end case;
   end process;

   with Opsel_in select
      carry_result <= shltemp when "000",
                      shrtemp when "001",
                      saltemp when "010",
                      sartemp when "011",
                      roltemp when "100",
                      rortemp when "101",
                      rcltemp when "110",
                      rcrtemp when "111",
                      (others => '0') when others;

   Result_out <= carry_result(15 downto 0);

   Carry_out <= carry_result(16);

end Behavioral;

 

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