I have codes a state table for a d-latch with clear and...

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<< Back to: FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)

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Question by Sreeni
Submitted on 3/19/2004
Related FAQ: FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)
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I have codes a state table for a d-latch with clear and preset in VHDL and tested to be working perfect. When I import the same stable to verilog, I get some mismatches in the expected ouptuts. By importing, I mean, creating the same state table entries in verilog. I have a test vector set of total 6560 vectors (all D, G, P, C input combinations over 0,1,x). 100% pass in vhdl, few fails in verilog. What is the reason? Does verilog require any special considerations in the state table (like edges etc.,?) -Sreeni

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