I have seen a verilog code in which in always's sensitivity...

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<< Back to: FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)

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Question by Manoj Karki
Submitted on 2/21/2004
Related FAQ: FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)
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I have seen a verilog code in which in always's sensitivity list there is a logical-or operator (\|\|) used instead of keyword (or).Can anyone mail me at manoj.karki@st.com that is it semantically right? Eg. always@(a \|\| b \|\| c).

Answer by Danno
Submitted on 12/24/2004
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No its not valid

Answer by Danno
Submitted on 12/24/2004
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No its not valid

Answer by Amit Srivastava
Submitted on 1/24/2005
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What a stupid question.. you dont know even this.

Answer by krs_1980
Submitted on 7/20/2005
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Hi manoj, The simulator tool might take it,but the synthesis tool wont take it.(you will get this error "unexpected event has occured in sensitivity list"). Thanks & Regards, Ravi...

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